Packaged semiconductor dies, including memory chips, microprocessor chips, logic chips and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, imager devices and other circuitry, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry.
Semiconductor manufacturers continually reduce the size of die packages to fit within the space constraints of electronic devices, while also increasing the functional capacity of each package to meet operating parameters. One approach for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. The dies in such vertically-stacked packages can be interconnected by electrically coupling the bond pads of the individual dies with the bond pads of adjacent dies using through-silicon vias (TSVs).
Another approach for increasing the power or capacity of a system is to vertically stack separate packages in a package-on-package assembly (POP assembly) in which each package can have one or more vertically stacked dies. Conventional POP assemblies have a bottom package that includes a bottom substrate and a bottom die, a top package that includes a top substrate with a top die, and a plurality of large solder balls that electrically connect the bottom and top packages. Although such POP assemblies are useful and relatively inexpensive to manufacture, they are not well suited for high-density applications that require a large number of input/output connections in a small footprint. For example, conventional through mold via and solder ball interconnects are limited to a pitch of 300 μm (e.g., spacing between interconnects of 300 μm) because large solder balls require a significant amount of lateral real estate. This is not suitable for many applications that require a pitch of no more than 150 μm. Therefore, it would be desirable to develop a POP assembly that can provide suitably tight pitches to accommodate advanced devices.